Memory speed and memory capacity continue to increase to meet the demands of system applications. Some of these system applications include mobile electronic systems that have limited space and limited power resources. In mobile applications, such as cellular telephones and personal digital assistants (PDAs), memory cell density and power consumption are issues for future generations. To address these issues, the industry is developing random access memories (RAMs) for mobile applications having low power consumption and including error correction.
Error correction code (ECC) calculates parity information and can determine if a bit has switched to an incorrect value. ECC can compare the parity originally calculated to the tested parity and make any corrections to correct for incorrect data values. In some cases, it is desirable to have ECC built directly onto a memory chip to provide greater memory chip reliability or to optimize other memory chip properties such as self refresh currents on low power dynamic RAMs (DRAMs). ECC circuitry, however, is typically associated with a large overhead due to additional memory elements used to store the parity information and additional logic circuitry used to calculate the parity information and error correction results. Typical ECC implementations may cost up to 50% of the memory chip area.